This invention is in the field of integrated circuits, and is more specifically directed to analog circuits including a variable voltage divider.
Despite the explosive trend toward the use of digital circuitry and digital operations in modern electronic systems, there remains a continuing need for analog circuitry in certain applications. For example, power supply controllers that control the power supply voltage applied to large scale integrated circuits, such as microprocessors and digital signal processors (DSPs), ultimately control an analog power supply voltage. Analog-to-digital converters (ADCs) remain necessary in signal acquisition functions, for example in the digitization of audio signals and in receiving network and broadband communications over hard-wired or wireless communications links. Analog circuitry also continues to be used in other control functions, such as motor control, power audio output functions, and the like.
The voltage divider is a fundamental building block in analog circuits, as it provides a desired voltage level that is derived from a power supply voltage or other higher voltage in the circuit. The simplest voltage divider arrangement, well known to even the most elementary of electrical engineering students, is the resistive voltage divider. In this circuit, the output voltage is taken from a tap at a node between two or more resistors connected in series, and is at a level corresponding to the ratio of resistances (i.e., the ratio of the resistance on one side of the tap relative to the total series resistance of the divider).
It is of course desirable to provide a voltage divider having a selectable, or variable, output voltage. Such a voltage divider can be used in real-time control applications, in tunable circuits, and in many other applications. FIG. 1 illustrates a conventional “code-controlled” voltage divider, which presents an output voltage that is selectable by the application of a digital control word (the digital “code”). In this conventional arrangement, the voltage divider includes upper resistor RREF connected between input node Vin and output node Vout. Resistors R0 through R5 are connected in parallel with one another, and in series with a respective corresponding one of switches S0 through S5, between output node Vout and ground. Each of switches S0 through S5 is controlled by a corresponding control line D0 through D5, to either connect its corresponding resistor R0 through R5 to ground (and thus into the voltage divider circuit) when closed, or to remove its corresponding resistor R0 through R5 from the circuit, when open. Typically, each switch S0 through S5 is implemented by way of an metal-oxide-semiconductor (MOS) transistor with its source-drain path connected between its corresponding resistor R0 through R5, and its gate receiving the control line D0 through D5, respectively. In this case, because transistor switches S0 through S5 operate digitally (on or off), the control lines D0 through D5 correspond to a digital control word, six bits wide in this example.
To obtain good resolution in the voltage divider ratio Vout:Vin (the voltage Vout being present at output node Vout, and the voltage Vin being present at input node Vin), the resistors R0 through R5 in the conventional code-controlled voltage divider of FIG. 1 are binary-weighted. For example, resistor R0 may have the largest resistance Rs0, with resistor R1 having a resistance R1 that is one-half of resistance Rs0, resistor R2 having a resistance of one-half of resistance Rs1, and so on. As such, the resistances Rs0 through Rs5 of resistors R0 through R5 are binary-weighted:
Resistance RelativeResistorto Rs0R0Rs0R1Rs0/21R2Rs0/22R3Rs0/23R4Rs0/24R5Rs0/25As a result, the digital word corresponding to the logic levels of control lines D0 through D5 will define the combination of resistors R0 through R5 that are included in the voltage divider.
In this binary-weighted case, one can readily derive the voltage ratio Vout:Vin from the value of the digital word on control lines D0 through D5. As fundamental in the art, the voltage divider ratio is determined by:             V      out              V      in        =            RREF                        R          par                +        RREF              =          1              1        +                  RREF                      R            par                              where resistance RREF is the resistance of resistor RREF, and where resistance Rpar is the resistance of those resistors R0 through R5 that are connected into the circuit by their respective switches S0 through S5 in response to the control word on control lines D0 through D5. For purposes of this example, the binary value of the levels on control lines D0 through D5 can be considered as a digital control word (or “code”), with control line D5 being the most significant bit, and with a “1” level on a control line D0 through D5 closing its corresponding switch S0 through S5.
The resistance of a network of parallel resistors can be readily found by considering that the conductance (i.e., the reciprocal of resistance) of a network of parallel resistors is the sum of the individual conductances. In this example, therefore:       1          R      par        =                    d        5            Rs5        +                  d        4            Rs4        +                  d        3            Rs3        +                  d        2            Rs2        +                  d        1            Rs1        +                  d        0            Rs0      where the values d5 through d0 correspond to the binary values on the respective control lines D5 through D0. Using the binary-weighting of the resistances Rs5 through Rs0 in the table, one can express the parallel conductance:             1              R        par              =                                        d            5                    ⁢                      2            5                          Rs0            +                                    d            4                    ⁢                      2            4                          Rs0            +                                    d            3                    ⁢                      2            3                          Rs0            +                                    d            2                    ⁢                      2            2                          Rs0            +                                    d            1                    ⁢                      2            1                          Rs0            +                                    d            0                    Rs0                ⁢                                  ⁢        or        ⁢                  :                                1              R        par              =                  (                                                            d                5                            ⁢                              2                5                                      +                                          d                4                            ⁢                              2                4                                      +                                          d                3                            ⁢                              2                3                                      +                                          d                2                            ⁢                              2                2                                      +                                          d                1                            ⁢                              2                1                                      +                          d              0                                Rs0                )            =              WORD        Rs0            where the control word WORD is the binary word of the logic levels on control lines D5 through D0, namely [d5 d4 d3 d2 d1 d0]. Placing this relationship back into the equation for the voltage divider ratio:             V      out              V      in        =      1          1      +                        RREF          ·          WORD                Rs0            
Accordingly, in the conventional example of the voltage divider of FIG. 1, the digital code WORD readily determines the voltage divider ratio, with the resolution of the divider ideally corresponding to the ratio of the resistance RREF to the largest resistance Rs0, and with the range of the ratio depending on the number of resistors in the lower part of the divider.
While this conventional voltage divider of FIG. 1 appears attractive for implementation into an integrated circuit, it has been observed, in connection with this invention, that practical limitations insert imprecision into this conventional circuit. One such limitation is the on-resistance presented by switches S0 through S5, which adds to the resistance in the associated parallel legs of the circuit. This additional resistance will, of course, disturb the binary weighting of the voltage divider, causing the output voltage Vout to not correspond to the desired ratio. According to conventional techniques, the on-resistance of switches S0 through 55 can be made insignificant relative to the resistances Rs0 through Rs5, but this requires the switching transistors to be extremely large, which is impractical for implementation into an integrated circuit.
Conversely, it is possible to include the switch impedance into the design, so that the combination of each resistor R0 through R5 and the impedance of its corresponding switch S0 through S5 is accounted for in the design (e.g., by reducing the resistance of each resistor by the on-resistance of its switch). However, it has been observed, in connection with this invention, that the differences in construction between integrated circuit resistors and switching transistors, such differences including different materials, different doping levels, and the like, result in different thermal coefficients of these devices. In other words, the precision of the voltage divider circuit may not hold over expected variations in temperature.